The present invention is directed to a DC to AC power converter circuit. More particularly, the present invention provides a high efficiency controller circuit that regulates power delivered to a load using a zero-voltage-switching technique. General utility for the present invention is found as a circuit for driving one or more Cold Cathode Fluorescent Lamps (CCFLs), however, those skilled in the art will recognize that the present invention can be utilized with any load where high efficiency and precise power control is required.
FIG. 1 depicts a convention CCFL power supply system 10. The system broadly includes a power supply 12, a CCFL driving circuit 16, a controller 14, a feedback loop 18, and one or more lamps CCFL associated with an LCD panel 20. Power supply 12 supplies a DC voltage to circuit 16, and is controlled by controller 14, through transistor Q3. Circuit 16 is a self-resonating circuit, known as a Royer circuit. Essentially, circuit 16 is a self-oscillating dc to ac converter, whose resonant frequency is set by L1 and C1, and N1-N4 designate transformer windings and number of turns of the windings. In operation, transistors Q1 and Q2 alternately conduct and switch the input voltage across windings N1 and N2, respectively. If Q1 is conducting, the input voltage is placed across winding N1. Voltages with corresponding polarity will be placed across the other windings. The induced voltage in N4 makes the base of Q2 positive, and Q1 conducts with very little voltage drop between the collector and emnitter. The induced voltage at N4 also holds Q2 at cutoff. Q1 conducts until the flux in the core of TX1 reaches saturation.
Upon saturation, the collector of Q1 rises rapidly (to a value determined by the base circuit), and the induced voltages in the transformer decrease rapidly. Q1 is pulled further out of saturation, and VCE rises, causing the voltage across N1 to further decrease. The loss in base drive causes Q1 to turn off, which in turn causes the flux in the core to fall back slightly and induces a current in N4 to turn on Q2. The induced voltage in N4 keeps Q1 conducting in saturation until the core saturates in the opposite direction, and a similar reversed operation takes place to complete the switching cycle.
Although the inverter circuit 16 is composed of relatively few components, its proper operation depends on complex interactions of nonlinearities of the transistors and the transformer. In addition, variations in C1, Q1 and Q2 (typically, 35% tolerance) do not permit the circuit 16 to be adapted for parallel transformer arrangements, since any duplication of the circuit 16 will produce additional, undesirable operating frequencies, which may resonate at certain harmonics. When applied to a CCFL load, this circuit produces a xe2x80x9cbeatxe2x80x9d effect in the CCFLs, which is both noticeable and undesirable. Even if the tolerances are closely matched, because circuit 16 operates in self-resonant mode, the beat effects cannot be removed, as any duplication of the circuit will have its own unique operating frequency.
Some other driving systems can be found in U.S. Pat. Nos. 5,430,641; 5,619,402; 5,615,093; 5,818,172. Each of these references suffers from low efficiency, two-stage power conversion, variable-frequency operation, and/or load dependence. Additionally, when the load includes CCFL(s) and assemblies, parasitic capacitances are introduced, which affects the impedance of the CCFL itself. In order to effectively design a circuit for proper operation, the circuit must be designed to include consideration of the parasitic impedances for driving the CCFL load. Such efforts are not only time-consuming and expensive, but it is also difficult to yield an optimal converter design when dealing with various loads. Therefore, there is a need to overcome these drawbacks and provide a circuit solution that features high efficiency, reliable ignition of CCFLs, load-independent power regulation and single frequency power conversion.
Accordingly, the present invention provides an optimized system for driving a load, obtains an optimal operation for various LCD panel loads, thereby improving the reliability of the system.
Broadly defined, the present invention provides A DC/AC converter circuit for controllably delivering power to a load, comprising an input voltage source; a first plurality of overlapping switches and a second plurality of overlapping switches being: selectively coupled to said voltage source, the first plurality of overlapping switches defining a first conduction path, the second plurality of overlapping switches defining a second conduction path. A pulse generator is provided to generate a pulse signal. Drive circuitry receives the pulse signal and controls the conduction state of the first and second plurality of switches. A transformer is provided having a primary side and a secondary side, the primary side is selectively coupled to the voltage source in an alternating fashion through the first conduction path and, alternately, through the second conduction path. A load is coupled to the secondary side of the transformer. A feedback loop circuit is provided between the load and the drive circuitry that supplies a feedback signal indicative of power being supplied to the load. The drive circuitry alternates the conduction state of the first and second plurality of switches, and the overlap time of the switches in the first plurality of switches, and the overlap time of the switches in the second plurality of switches, to couple the voltage source to the primary side based at least in part on the feedback signal and the pulse signal.
The drive circuitry is constructed to generate a first complimentary pulse signal from the pulse signal, and a ramp signal from the pulse signal. The pulse signal is supplied to a first one of the first plurality of switches to control the conduction state thereof, and the ramp signal is compared with at least the feedback signal to generate a second pulse signal, where a controllable conduction overlap condition exists between the conduction state of the first and second switches of the first plurality of switches. The second pulse signal is supplied to a second one of the first plurality of switches and controlling the conduction state thereof The drive circuitry further generates a second complimentary pulse signal based on the second pulse signal, wherein said first and second complimentary pulse signals control the conduction state of a first and second ones of the second plurality of switches, respectively. Likewise, a controllable conduction overlap condition exists between the conduction state of the first and second switches of the second plurality of switches.
In method form, the present invention provides a method for controlling a zero-voltage switching circuit to deliver power to a load comprising the steps of supplying a DC voltage source; coupling a first and second transistor defining a first conduction path and a third and fourth transistor defining a second conduction path to the voltage source and a primary side of a transformer; generating a pulse signal to having a predetermined pulse width; coupling a load to a secondary side of said transformer; generating a feedback signal from the load; and controlling the feedback signal and the pulse signal to determine the conduction state of said first, second, third and fourth transistors.
In the first embodiment, the present invention provides a converter circuit for delivering power to a CCFL load, which includes a voltage source, a transformer having a primary side and a secondary side, a first pair of switches and a second pair of switches defining a first and second conduction path, respectively, between the voltage source and the primary side, a CCFL load circuit coupled to the secondary side, a pulse generator generating a pulse signal, a feedback circuit coupled to the load generating a feedback signal, and drive circuitry receiving the pulse signal and the feedback signal and coupling the first pair of switches or the second pair of switches to the voltage source and the primary side based on said pulse signal and said feedback signal to deliver power to the CCFL load.
Additionally, the first embodiment provides a pulse generator that generates a pulse signal having a predetermined frequency. The drive circuitry includes first, second, third and fourth drive circuits; and the first pair of switches includes first and second transistors, and the second pair of switches includes third and fourth transistors. The first, second, third and fourth drive circuits are connected to the control lines of the first, second, third and fourth transistors, respectively. The pulse signal is supplied to the first drive circuit so that the first transistor is switched in accordance with the pulse signal. The third drive circuit generates a first complimentary pulse signal and a ramp signal based on the pulse signal, and supplies the first complimentary pulse signal to the third transistor so that the third transistor is switched in accordance with the first complimentary pulse signal. The ramp signal and the feedback signal are compared to generate a second pulse signal. The second pulse signal is supplied to the second drive circuit so that the second transistor is switched in accordance with the second pulse signal. The forth driving circuit generates a second complementary pulse signal based on the second pulse signal and supplies the second complementary pulse signal to the fourth transistor so that the fourth transistor is switched in accordance with the second complimentary pulse signal. In the present invention, the simultaneous conduction of the first and second transistors, and the third and fourth transistors, respectively, controls the amount of power delivered to the load. The pulse signal and the second pulse signal are generated to overlap by a controlled amount, thus delivering power to the load along the first conduction path. Since the first and second complementary pulse signals are generated from the pulse signal and second pulse signal, respectively, the first and second complementary pulse signals are also generated to overlap by a controlled amount, power is delivered to the load along the second conduction path, in an alternating fashion between the first and second conduction paths.
Also, the pulse signal and first complementary pulse signal are generated to be approximately 180xc2x0 out of phase, and the second pulse signal and the second complementary signal are generated to be approximately 180xc2x0 out of phase, so that a short circuit condition between the first and second conduction paths is avoided
In addition to the converter circuit provided in the first embodiment, the second embodiment includes a flip-flop circuit coupled to the second pulse signal, which triggers the second pulse signal to the second drive signal only when the third transistor is switched into a conducting state. Additionally, the second embodiment includes, a phase-lock loop (PLL) circuit having a first input signal from the primary side and a second input signal using the feedback signal. The PLL circuit compares the phase difference between these two signals and supplies a control signal to the pulse generator to control the pulse width of the pulse signal based on the phase difference between the first and second inputs.
In both embodiments, the preferred circuit includes the feedback control loop having a first comparator for comparing a reference signal with the feedback signal and producing a first output signal. A second comparator is provided for comparing said first output signal with the ramp signal and producing said second pulse signal based on the intersection of the first output signal and the ramp signal. The feedback circuit also preferably includes a current sense circuit receiving the feedback signal and generating a trigger signal, and a switch circuit between the first and second comparator, the switch circuit receiving the trigger signal and generating either the first output signal or a predetermined minimum signal, based on the value of the trigger signal. The reference signal can include, for example, a signal that is manually generated to indicate a desires power to be delivered to the load. The predetermined minimum svoltage signal can include a programmed minimum voltage supplied to the switches, so that an overvoltage condition does not appear across the load.
Likewise, in both embodiments described herein, an overcurrent protection circuit can be provided that receives the feedback signal and controls the pulse generator based on the value of said feedback signal. An overvoltage protection can be provided to receive a voltage signal from across the load and the first output signal and compare the voltage signal from across the load and the first output signal, to control the pulse generator based on the value of the voltage signal from across the load.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to preferred embodiments and methods of use, the present invention is not intended to be limited to these preferred embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be limited as only set forth in the accompanying claims.
Other features and advantages of the present invention will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and wherein: